Multi-chip power modules pack several SiC chips in parallel to handle higher currents. In an ideal world, each chip carries its fair share of the load. In practice, small differences in chip parameters or bonding wire connections can cause uneven current distribution — with consequences for reliability and safe operating area.
Detecting these asymmetries is not straightforward. Standard measurements like drain-source voltage, gate-source voltage, or total load current show little to no change even when current distribution is significantly uneven. A different approach is needed.
In a study presented at ISPSD 2026, researchers from the University of Bremen and Kyushu University show that the Kelvin Source (KS) path offers exactly that. In a three-chip SiC half-bridge module, the KS current of individual chips responds measurably to changes in source impedance — even when the total load current looks perfectly normal. As bonding wires are progressively removed from one chip, the KS current shifts detectably while the standard measurement signals remain essentially flat. The method works down to complete chip failure — at which point the module was still functional, but the remaining chips were operating under increased stress.
Fig. 1: Detecting current asymmetries in multi-chip SiC power modules using the Kelvin source path.
Two types of M-Shunts were central to the measurement setup: one for load current detection, and a second placed in the KS path as a dedicated current sensor. The combination enabled to resolve the small, fast transient signals in the KS path alongside the main switching waveforms — a measurement challenge that conventional current probes would struggle with given the bandwidth and footprint requirements.
The results suggest a viable route to detecting design issues during development as well as degradation during operation — without requiring access to individual chip terminals beyond the KS path.
Related publication
The underlying research was published at ISPSD 2026.
