Category: Application

  • Detecting Bond Wire Lift-Off with Machine Learning – Using the M-Shunt Kelvin-Source Current

    Can a healthy chip be told apart from a degraded one just by feeding its switching waveform into a neural network? A new collaboration between Kyushu University and IALB shows that it can — and that the Kelvin-source current is the one input the network can trust even when temperature gets in the way.

    Bond wire lift-off is one of the classic wear-out mechanisms in power modules: as wires fatigue and detach, the source resistance and inductance of the affected chip rise, current sharing between parallel devices shifts, and the switching waveform changes shape. Machine-learning classifiers trained on such waveforms have already shown promise for detecting lift-off without any dedicated monitoring circuit — but almost always for a single chip. Real power modules, however, are built from several chips in parallel, and it was unclear whether the same approach would still work once device-to-device mismatch and temperature differences start shaping the waveform as well.

    The study addresses exactly that. Two discrete SiC-MOSFETs were connected in parallel and put through double-pulse tests, with the M-Shunt measuring the load current and a Mini-M-Shunt measuring the Kelvin-source current. Source bond wires were then cut in a controlled sequence — from all four intact down to just one remaining — to simulate four stages of degradation, from healthy to heavily damaged. A convolutional neural network was trained to classify the degradation stage from the switching waveform, and the experiment was repeated across three current-balance conditions, obtained by pairing devices with different threshold voltages.

    The gate voltage and the Kelvin-source current turned out to be the most dependable inputs, both reaching close to 100 % classification accuracy regardless of current imbalance or which of the two devices was evaluated. The drain-source voltage and load current, by contrast, were far less consistent — drain-source voltage accuracy collapsed to around 25–30 % during turn-off, and load-current accuracy dropped to about 52 % for one device during turn-on, simply because degradation left too faint a mark on those particular waveform segments.

    The more demanding test came next: could rising temperature alone — with no wires cut at all — fool the network into reporting degradation? For the gate voltage during turn-on, the answer was yes: its ringing amplitude fades with temperature in much the same way it fades with wire lift-off, and the classifier’s healthy-state accuracy dropped to almost 0 % once the device was heated. The Kelvin-source current showed no such confusion. Across every temperature step tested, it kept a healthy-state classification rate of around 99–100 %, correctly recognising an undamaged device as undamaged even as its temperature rise by close to 60 °C.

    That combination — high sensitivity to genuine degradation and near-total immunity to temperature-driven false alarms — is what makes the Kelvin-source current a particularly promising basis for machine-learning-based condition monitoring in parallel-chip power modules, without adding dedicated sensing hardware beyond the M-Shunt itself.

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  • When Heat Looks Like Damage: Separating Temperature and Degradation Effects with the M-Shunt

    Bond wire lift-off and rising junction temperature both disturb the current sharing of parallel-connected SiC-MOSFETs — and in steady state, they can look surprisingly alike. Telling them apart matters: mistaking a harmless temperature swing for degradation (or the other way round) undermines any real-time health monitoring scheme built on the Kelvin-source current.

    A new study by researchers from the University of Bremen and Kyushu University, to be presented at ICSCRM 2026 in Yokohama, investigates exactly this ambiguity — and shows how to resolve it.

    Parallel SiC-MOSFETs are the standard way to scale up the current-carrying capability of a power module. But unavoidable mismatches between chips, together with layout-driven differences in parasitic inductance, mean the current is rarely shared perfectly. The Kelvin-source (KS) current — the small balancing current that flows through the shared source connection of two paralleled devices — has already been shown to reveal such asymmetries, including the very first stages of bond wire lift-off, well before they show up in the load current. The open question this work addresses is how a second disturbance, junction temperature, interacts with that same signal.

    Using two SiC-MOSFETs in TO-247-4L packages, one device was deliberately heated with a soldering iron mounted to its backplate while the KS current was captured with M-Shunts placed in both the load and the KS path. As the heated device’s junction temperature rises, its threshold voltage drops while its on-state resistance increases — two effects that pull the balancing current in opposite directions during a single switching event. The result is a distinctive transient signature: the KS current first swings towards one polarity as the lower threshold voltage lets the heated device turn on earlier, then reverses towards the opposite polarity as its higher on-state resistance takes over in steady state.

    Bond wire lift-off behaves quite differently. Removing bond wires increases both the source resistance and inductance of a device, which simply shifts the KS current waveform in one direction, in both the transient and steady-state phases, without the reversal seen for temperature. While the steady-state values for both effects can end up looking similar, the transient shape does not — the opposite-direction peak is a reliable fingerprint of a temperature disturbance rather than genuine degradation.

    The findings point to the transient KS current, not just its steady-state value, as the more robust basis for real-time health monitoring — and the authors suggest that an AI-based evaluation of the signal is a promising next step towards distinguishing the two effects reliably in the field.

    Related publication The underlying research will be presented at ICSCRM 2026, Yokohama, Japan (27 September – 2 October 2026).

  • Why a Faster Sensor Doesn’t Always Mean a Faster Reaction

    A current sensor’s datasheet bandwidth describes how fast it can see a transient. It says very little about how fast a system built around that sensor can act on one — and for any protection or safety function with a hard time budget, that second number is the one that matters.

    Once a shunt is small and accurate enough to sit inside a control loop rather than on a lab bench, its job changes. It stops being an instrument that records a waveform for later analysis, and becomes a component whose output has to cross a threshold and trigger a reaction — a short-circuit trip, a breaker, a safety stop — before the fault has done damage. In that role, three delays stack up between the current event and the reaction: the sensor’s own transfer behaviour, whatever filtering is needed to make the signal usable, and the threshold margin that has to be added if the signal is not trustworthy close to that threshold.

    That third term is easy to overlook. A sensor whose transfer function rings or deviates by tens of percent inside its own bandwidth forces the trip threshold to sit further away from the real fault level, and often needs a blanking window on top, simply to avoid false trips on ordinary switching transients. Fidelity and reaction time are not competing goals here — fidelity is what buys the margin back.

    Bandwidth on paper vs. bandwidth that acts

    This is also why the 3 dB figure on a shunt’s datasheet is a limited guide. It is normally derived from a vector network analyser measurement, and a VNA excites a shunt differently from how it operates in a power circuit: both the load path and the measurement path are forced into one closed loop, so parasitics that belong exclusively to the load path show up in the measured response even though they don’t limit what the measurement path can actually resolve.

    We demonstrated this directly by mechanically shortening a commercial coaxial shunt’s outer lead — a change confined entirely to the load path — and watched the measured transmission flip from inductive to capacitive behaviour, despite the internal coupling geometry being untouched. The datasheet number moved; the sensor’s real measurement mechanism did not. What a fault-detection circuit needs validated is the time-domain response, not the VNA curve.

    (Full methodology: H. Lutzen, J. Müller, V. Polezhaev, T. Huesgen and N. Kaminski, “From Insight into Bandwidth to Fast-Transient Precision: Diamond M-Shunts for Wideband Current Measurement,” CIPS 2026, Dresden, Germany.)

    Coupling strength is a design knob, not a parasitic

    The Diamond-M-Shunt’s rhombic split-coupling geometry makes the electromagnetic coupling between load and measurement path an explicit, adjustable parameter — set by the widening angle of the traces. We built and measured variants from 0° to 5°. A 4° angle gave the highest nominal 3 dB bandwidth; a 5° angle gave the lowest in-band deviation, holding within ±10 %, and visibly cleaner double-pulse waveforms. For measurement work, 5° is the right answer — the higher bandwidth number at 4° comes with distortion that a VNA curve alone won’t show.

    That trade-off is worth pushing further as a thought experiment. If a circuit only needs to know that di/dt has crossed a limit — not reconstruct the waveform — then over-coupling beyond the 5° compensation point stops being a defect. It emphasises exactly the fast components an edge detector cares about, at the cost of amplitude accuracy nobody in that role needs. We have not characterised an over-coupled geometry for detection latency specifically, and it would need its own figures of merit rather than a 3 dB number. But it illustrates the underlying point: coupling strength should be chosen for what the output is used for — plotted, or acted on — and today almost no shunt is designed with the second case in mind.

    Small enough to sit at the fault

    None of this helps if the sensor can’t physically be where the fault happens. The Mini-M-Shunt line closes that gap: bandwidths beyond 300 MHz and residual insertion inductance below 1 nH in 6 × 12 mm and 6 × 18 mm devices on standard SMD footprints, with continuous current capability of 7–10 A and pulse tolerance above 1 kA. Their surface-to-volume ratio also means the usual adiabatic datasheet estimate is conservative — thermal coupling to the PCB and vias sustains meaningfully higher currents in practice.

    The practical consequence is placement. A Mini-M-Shunt fits directly into a critical current path, a Kelvin-source path, or inside a power module — measuring the current of one device rather than the aggregate at the DC link. That matters because fault signatures that are obvious at the device are frequently invisible further out: our Kelvin-source measurements on bond wire lift-off show dynamic current asymmetries at the individual switch that a load-current measurement alone would miss.

    (Full methodology: H. Lutzen, J. Müller, V. Polezhaev, S. Clausner, T. Huesgen and N. Kaminski, “Pushing Miniaturisation in Current Sensing: Ultra-Compact Mini-M-Shunts for Even Faster Transients,” PCIM Europe 2026, Nuremberg, Germany.)

    Where the budget still has room

    Any system with a hard reaction-time budget — short-circuit protection in SiC/GaN converters, solid-state breakers, battery disconnect, or the drive-side safety functions that set the allowed operating envelope in motion control — inherits a detection term inside that budget. The mechanical and control contributions have mostly been optimised for years. Detection latency has largely been treated as a fixed cost of the sensor you happen to have. We don’t think it has to be.

    Related publications

  • Detecting Bond Wire Lift-Off in Parallel SiC-MOSFETs — with the M-Shunt Kelvin-Source Current

    Bond wire lift-off is one of the classic degradation mechanisms in power semiconductor packages, driven by thermomechanical stress from repeated load cycling. As wires detach from the chip’s source metallisation, the parasitic source inductance and resistance increase — with direct consequences for switching behaviour, and, in parallel-connected devices, for how the current is shared between chips.

    A study presented at ISPS 2025 by researchers from the University of Bremen, METU and Kyushu University investigates this effect on discrete TO-263 packaged SiC-MOSFETs, using the M-Shunt to capture both the load current and, for the first time in this setup, the Kelvin-source (KS) current.

    For a single device, removing bond wires one by one — simulating progressive lift-off — increases the source inductance and resistance, confirmed by Ansys Q3D and LTspice modelling of the package. The measured effect is consistent: the rate of change of current and voltage during turn-on drops, and the switch takes measurably longer to turn on, with total switching losses rising as more wires are removed.

    In two parallel-connected devices, the same effect shows up as a current imbalance. As bond wires are progressively removed from one of two paralleled MOSFETs (Q1*), that device’s current slows down and shifts to its unaffected neighbour (Q2) — which then has to carry more current and absorbs the additional switching losses. This drain-current imbalance is measurable, but at low numbers of removed bond wires it is initially masked by ordinary chip-to-chip tolerances, so it only becomes a reliable indicator once enough bond wires are gone.

    The Kelvin-source current is more sensitive. Because the KS path is decoupled from the load loop but shared between both devices, any difference in source impedance between the two chips drives a measurable current through this shared connection — increasing systematically with every bond wire removed, and clearly identifiable from the very first removed wire, regardless of which position on the chip it is removed from.

    To resolve this, the PCB carries four M-Shunts: two in the load path, capturing the individual drain currents of Q1* and Q2, and two more, dedicated units in the Kelvin-source path. The low self-inductance and compact footprint of the M-Shunt make it possible to integrate all four sensors into a PCB layout designed for symmetric, low-inductive switching — without the shunts themselves distorting the fast transients they are meant to measure.

    The results point towards Kelvin-source current monitoring as a practical building block for health monitoring of power semiconductors — a clean, low-effort signal that can flag the very first bond wire lift-off well before it is visible in standard drain-current or voltage measurements.

    Related publication The underlying research was published at ISPS 2025.

  • Detecting Current Asymmetries in Multi-Chip SiC Power Modules — with the M-Shunt

    Multi-chip power modules pack several SiC chips in parallel to handle higher currents. In an ideal world, each chip carries its fair share of the load. In practice, small differences in chip parameters or bonding wire connections can cause uneven current distribution — with consequences for reliability and safe operating area.

    Detecting these asymmetries is not straightforward. Standard measurements like drain-source voltage, gate-source voltage, or total load current show little to no change even when current distribution is significantly uneven. A different approach is needed.

    In a study presented at ISPSD 2026, researchers from the University of Bremen and Kyushu University show that the Kelvin Source (KS) path offers exactly that. In a three-chip SiC half-bridge module, the KS current of individual chips responds measurably to changes in source impedance — even when the total load current looks perfectly normal. As bonding wires are progressively removed from one chip, the KS current shifts detectably while the standard measurement signals remain essentially flat. The method works down to complete chip failure — at which point the module was still functional, but the remaining chips were operating under increased stress.

    Fig. 1: Detecting current asymmetries in multi-chip SiC power modules using the Kelvin source path.

    Two types of M-Shunts were central to the measurement setup: one for load current detection, and a second placed in the KS path as a dedicated current sensor. The combination enabled to resolve the small, fast transient signals in the KS path alongside the main switching waveforms — a measurement challenge that conventional current probes would struggle with given the bandwidth and footprint requirements.

    The results suggest a viable route to detecting design issues during development as well as degradation during operation — without requiring access to individual chip terminals beyond the KS path.

    Related publication
    The underlying research was published at ISPSD 2026.

    Fullpaper link: ISPSD 2026